With the development of fabricating process for CMOS integrated circuits and the reduction in critical dimension, novel materials and processes have been applied to device fabricating processes improve the performance of devices. In a back end process of integrated circuits, Copper (Cu) lines are used to replace Aluminum (Al) lines, and the interconnection resistance is greatly reduced. At the same time, the use of a porous low-k dielectric material can realize a dielectric constant of 2.5 or less. These techniques can effectively reduce RC delay in integrated circuits.
Since Cu is prone to diffuse, a Cu diffusion barrier layer is deposited after a chemical mechanical polishing of a back end Cu layer, and then a low-k dielectric material is deposited, so as to avoid the Cu diffusion into the low-k dielectric material. In technology nodes of 28 nm or larger, this Cu diffusion barrier layer is usually formed by a thin nitrogen-doped silicon carbide (NDC, k˜5.3) film. In technology nodes of 28 nm or less, a diffusion barrier layer of cobalt film is introduced which is formed by CVD. The diffusion barrier layer of cobalt can not only block the diffusion of Cu, but also prevent the moisture in air from penetrating the Cu layer during fabrication. The introduction of the cobalt film indicates that the thickness of the nitrogen-doped silicon carbide (NDC) film is reduced, which facilitates reducing the overall effective k value. Besides, cobalt has excellent adhesion ability with respect to Cu, and the reliability of products can be significantly improved.
However, a more amount of cobalt deposited on the dielectric layer means a larger leakage current of between Cu interconnection lines. Thus, it is urgent to explore a method for depositing cobalt, in which the amount of cobalt deposited on a porous dielectric layer is as small as possible, namely, deposition selectivity is as much as possible.